LeadSoc Part 1 of 2 · LeadSoc Technical Blog Series Static Timing Analysis Fundamentals and the SDC File VLSI Design · Timing Closure · Synopsys Design Constraints (SDC) Introduction A…

LeadSOC Home » Blog » RISC-V Processor Subsystem Co-Verification Co-Verification of a RISC-V Processor Subsystem: From Bootcode to Peripheral Access RISC-V Verification · Hardware/Software Co-Verification · SoC Bring-up Introduction Designing…

RISC-V Processor Subsystem Design: Peripherals, DMA, MMU & Cache Hierarchy | LeadSOC Home » Blog » RISC-V Processor Subsystem Design Developing a RISC-V Processor Subsystem: Integrating Peripherals, Memory, DMA, Interrupts,…

AI-Enabled EDA: Transforming SoC Design from Simulation to Signoff | LeadSOC LeadSOC Home » Blog » AI-Enabled EDA Transforming SoC Design Productivity from Simulation to Signoff with AI Enablement in…

Radar Signal-Processing SoC: Architecture, Applications & Verification | LeadSOC LeadSOC Home » Blog » Radar Signal-Processing SoC Radar Signal-Processing System-on-Chip: Architecture, Applications, Design Approach and Verification RF & Mixed-Signal Design…

Automotive Gas & Pressure Sensor SoCs: Building the Sensing Intelligence into Vehicles | LeadSOC LeadSOC Home » Blog » Automotive Gas & Pressure Sensor SoCs Building the Sensing Intelligence into…