VLSI Design Services
End to End VLSI Design Services
LeadSoC Advantage in End to End VLSI Design Services
FPGAs, ASICs and SoCs are being increasingly used to implement cutting edge solutions for multiple markets
Telecom, Automotive, IOT, specialized Healthcare appliances, gateways, router leverage these solutions extensively
LeadSoC advantage addresses all 3Ps of SoC Design Requirements=> Lower Price, Lower Power and Higher Performance
LeadSoC is one stop solution to address all facets of VLSI Design =>Digital frontend & backend, Analog Design & Layout, Memory Design & Layout etc.
LeadSoC has strong track record of successful VLSI design services to the leading OEM’s, ODM’s and chipmakers
LeadSoC VLSI advantage is boosted by in-house VLSI Training with Labs to groom talent.
IP Design, SOC Integration
Low power , multi clock design implementation
PCIe, Ethernet, SAS, USB Sub Systems
SOC/Sub System integration
RTL QC Checks Ex LINT, CDC & Audit
Timing constrains, Synthesis and STA
Power aware design
IP / SOC Verification & Emulation
Feature extraction ,test plan creation and coverage plan based in UVM
Complete Verification Environment bring up from scratch and flow
Setup of palladium, Zebu and FPGA verification
GLS and UPF flow setup
X propagation clean up and GLS sign off
Multi core SoC Expertise in various processors as ARM Cortex M/R series and RISC V , ARC cores.
Experienced in various complex IP’s such as USB, PCIE, Ethernet , Graphics and MIPI and memory controller subsystem
BFM model generation
UVM, OVM, SV / C/ C++ verification approach from scratch
FPGA Design / ASIC Emulation
System architecture and FPGA selection for Xilinx, Intel, Microsemi, Lattice
Software hardware partitioning
Microarchitecture including FPGA vendor provided IPs, custom IPs and glue logic.
Retarget ASIC code to FPGA.
Design synthesis, P&R and timing closure.
Multi boot, partial configuration , remote system update.
Board bring up, FPGA design validation using test software, protocol analyzers and lab equipment.
Hier – Chip-TOP | Flat – Chips | Blocks
Hier- Floorplan/ Partition
Synthesis & DFT
ATPG, MBIST BSCAN, JTAG Test Verification
Analog & Custom Design
Analog/Mixed signal Verification of
IP/Subsystem/ full chip verification of complex mixed signal ASICs.
Modelling of Analog and Mixed signal blocks using Verilog
AMS/ Wreal/ RNM
Expertise in setup of Digital mixed signal environment using custom verification flows such as UVM AMS.
RF & Hardware Design
RF subsystem design
Board design and enclosure design
Schematic Entry & PCB Design
Component selection and CAD library management
Post Silicon Support
Prototype and volume manufacturing
Post silicon Testing and Qualification
Test Automation and ATE support
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