Careers (VLSI)

Associate Engineer
REQ001 | Exp.: 1-2 Yr | Bangalore
Physical Design Engineer
REQ002 | Exp.: 2-4 Yr | Bangalore
Sr Engineer/Lead/Engineering Manager - Physical Design Engineer
REQ003 | Exp.: 4-12 Yr | Bangalore
Floorplan lead
REQ004 | Exp.: 4-12 Yr | Bangalore
STA Lead : Static Timing Analysis
REQ004 | Exp.: 4-12 Yr | Bangalore
ASIC verification Engineer
REQ004 | Exp.: 2-10 Yr | Bangalore
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Job Description

B.Tech Electronics/Electrical/Computer Science Engineering with minimum of 6 months training in VLSI courses with high scores. Or M.Tech in Electronics/VLSI/CAD with good % of marks

Skills Required

  • Strong analytical/Aptitude skills.
  • Very good programming & scripting skills.
  • Excellent skills in Unix, Shell.
  • Good communication & very good attitude.
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Job Description

B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 2 year of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at block level for multiple tape outs. With Block level hands on experiences in most of the following.

Skills Required

  • Block level floor planning, power planning and IR drop analysis.
  • Timing closure with Xtalk and OCV
  • Multimode multi corner optimization and closure.
  • Clock tree synthesis and advanced clock tree implementation.
  • Blocks sizes upward of 400K Instances to 2M Instances.
  • Block level timing closure with sign off STA.
  • Block level ECO implementation involving netlist level logical changes.
  • Scripting experience in Perl/TCL.
  • Excellent debugging skills in implementation issues and ability to come up with creative solutions.
  • Low power technologies exposure.
  • Technologies from 28nm and below.
  • Physical Verification experience in advance nodes.
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Job Description

B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 1 tape out. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage

Skills Required

  • Top level die size estimation, floor planning, power estimation , power planning .
  • IO Planning and package compatibility sign off.
  • Netlist and constraint sign in checks and validation.
  • Prime time constraint development at full chip level and clean up.
  • Design implementation environment setup.
  • Static and Dynamic power analysis at the top level.
  • Netlist to GDS II implementation at chip level.
  • Hierarchical chip planning, block planning , block level constraint development, hierarchical clock tree implementation, block integration and chip finishing.
  • Multimode multi corner optimization and closure at top level.
  • Clock tree synthesis and advanced clock tree implementation at full chip level.
  • Handling of PLL, TXR, DDR and other analog components during implementation.
  • IO ring customization for multi IO designs.
  • Full chips upward of 1M Instances to 20M+ instances.
  • Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
  • Top level ECO implementation strategy development for netlist ,RTL and timing level changes
  • Scripting experience in Perl/TCL.
  • Flow customization and fine tuning for Power , Performance, Area.
  • Exposure to DFM and DFM compatible implementation.
  • Excellent debugging skills in implementation issues and ability to come up with creative solutions .
  • Exposure to designs critical for power, area and timing at the same time.
  • Technologies from 28nm and below.
  • Exposure to Physical design project planning and execution.
  • Technical leadership and ability to mentor and make the team deliver.
careers@leadsoc.com Mail

Job Description

B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of strong, hands on Physical Design experience. Must have hands in hierarchical partitioning of internal hard macros/blocks from either chip top or sub system. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage

Skills Required

  • hierarchical partitioning of internal hard macros/blocks from either chip top or sub system
  • Top level die size estimation, floor planning, power estimation , power planning .
  • Handling of PLL, TXR, DDR and other analog components during implementation.
  • Scripting experience in Perl/TCL.
  • Flow customization and fine tuning for Power , Performance, Area.
  • Exposure to DFM and DFM compatible implementation.
  • Excellent debugging skills in implementation issues and ability to come up with creative solutions .
  • Exposure to designs critical for power, area and timing at the same time.
  • Technologies from 28nm and below.
  • Exposure to Physical design project planning and execution.
  • Technical leadership and ability to mentor and make the team deliver.
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Job Description

B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of strong, hands on block/sub HM level Timing closure or chip top level timing closure. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage

Skills Required

  • Netlist and constraint sign in checks and validation.
  • Prime time constraint development at full chip level and clean up.
  • Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.
  • Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
  • Top level ECO implementation strategy development for netlist, RTL and timing level changes
  • Scripting experience in Perl/TCL.
  • Excellent debugging skills in implementation issues and ability to come up with creative solutions .
  • Technologies from 28nm and below.
  • Technical leadership and ability to mentor and make the team deliver.
careers@leadsoc.com Mail

Job Description

Candidate will be responsible for IP Level Verification. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements.

Skills Required

  • Minimum Qualifications Desired skills set includes Verification aptitude, Expertise in SV-UVM, Coverage Closure, RTL debug till root causing, Low Power Verification/UPF, GLS, Assertions based verification, DPI, Testbench building.
  • Familiarity with bus protocols like AHB, AXI, ARM based system architecture, emulation (ex: Veloce), Scripting language like perl
  • Excellent problem solving skills and strong communication and team work skills are mandatory
  • Preferred Qualifications Formal Verification concepts and working knowledge, C/C++, working knowledge on camera are plus

Education Requirements Required:

  • BE/BTech/ME/MTech/MS Electrical Engineering and/or Electronics, Vlsi from reputed university with preferably distinction

Careers (Software)

Linux Drivers and User space
REQSS001 | Exp.: 3-8 Yr | Bangalore, Hyderabad, Chennai
Machine Learning / Data Analytics
REQSS002 | Exp.: 1-3 Yr | Bangalore
Machine Learning / Senior Data Analyst
REQSS003 | Exp.: 3-6 Yr | Bangalore
Software Test Engineer (Yocto/Linux)
REQSS004 | Exp.: 2-8 Yr | Hyderabad
Math library Software Engineers
REQSS005 | Exp.: 3-15 Yr | Bangalore
Mobile Modem (3G/4G/5G)
REQSS006 | Exp.: 3-15 Yr | Bangalore, Hyderabad
careers@leadsoc.com Mail

Job Description

B.E/M.E/M.Tech in EEE/ECE/CSE with minimum of 3~6 years of strong, hands on embedded software development & validation experience in Linux environment with Linux device driver, API development for SQA/Validation activity

Skills Required

  • Experience in developing, porting, validating and debugging Linux device drivers, boot loaders, board support package (BSP)
  • Experience in ARM based SoC software development
  • Strong experience in Linux kernel, Driver porting/development experience essential with Advanced C
  • Should have worked on the following or any of the following Driver experience (CMOS Camera drivers (MIPI/Parallel/LVDS), GPU, PCIe, DDR, Ethernet, USB, UFS)
  • Good knowledge on Microprocessor internals and working of SOC peripherals (Timers, Interrupts, Clock modules, Cache, Memory Controllers)
  • Good experience in C/C++, Python & Shell scripting language
  • Solid hands on expertise in using test equipment used in validation (Logic Analyzers, High Speed Oscilloscope, signal generators, Protocol Analyzers, Spectrum Analyzer for measurement and debugging issues / Network Analyzer)
  • Good Debugging skills, Problem solving ability & communication skills
careers@leadsoc.com Mail

Job Description

Work in a highly analytical, results-oriented environment. Proven analytical and quantitative skills and an ability to perform research and analysis to back up assumptions. Managing metrics and insights for improving performance. Mine and analyze data from machine log data to drive optimization, reduce failures or solve any other business use case.

Skills Required

  • Should be comfortable working with SQL, Large Datasets and Excel
  • 2+ years of work experience as a Data analyst
  • Engineering graduate, with a B.E./B.Tech Degree
  • Working proficiency of machine learning techniques like Bayesian, Decision Trees, Neural Networks, Ensemble, Random Forest, KNN etc. Proficiency in SQL
  • Knowledge in Python & R a plus
  • An ability to think quantitatively and qualitatively about operating processes and outcomes Strong interpersonal
  • Proven ability to define effective, efficient, and scalable processes and drive continuous improvement through root cause identification and defect elimination skills-Analytics, Market Research Qualifications-BE/B.TechExperience-2 to 3 Years
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Job Description

    Provide analytical and data-driven decision-making support for key projects. Develop new insights and analyses that informs and aids key business decisions. Provide reporting and performance monitoring using data drawn from diverse sources. Execute quantitative analyses that translate data into actionable insights.

    Skills Required

    • Good client management skills with a strong grasp of both technical and business perspectives
    • 5+ years of experience performing quantitative/statistical analysis, preferably for an internet or technology company
    • Experience in using tools like Tableau for creating dashboards, reports and data exploration (strongly preferred)
    • Strong hands-on experience with SQL, data warehousing, data modeling, dashboarding and reporting, involving very large datasets and multiple data sources, with ability to interpret data and produce meaningful insights.
    • Working proficiency of machine learning techniques like Bayesian, Decision Trees, Neural Networks, Ensemble, Random Forest, KNN etc.
    • Comfortable manipulating, transforming, and analyzing complex, high-volume, high-dimensionality data from varying sources
    • Extensive experience querying large, complex data sets
    • Experience automating analysis using analytics packages in languages like R or Python
    • Ability to execute research projects, and generate practical results and recommendations
    • Proven ability to work in a fast-paced environment, and to meet changing deadlines and priorities on multiple simultaneous projects
    • Enjoy working in both individual and team settings
    • BE/BTech Comp Sci, Engineering, with advanced degrees strongly preferred
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Job Description

B.E / B.Tech in Electronics/Computer Science with minimum of 2~8 years of strong, hands on C/C++, BASH, Python programming and debugging skills

Skills Required

  • Experience with the Yocto Project
  • Experience implementing Linux applications and daemons, familiarity with embedded Linux a plus AND Linux kernel and user-space development
  • Strong familiarity with the Linux operating system internals, kernel module, networking development a plus
  • Develop or customize board support packages (BSP)
  • Experience with source control (Git)
  • Strong analytical and problem-solving skills Excellent communication skills
  • Work along with Yocto and PetaLinux Development team to understand the features, the code base, Identify test cases, use Yocto autobuilder, ptest mechanism to fix issues and work with regressions team to get the test cases added in daily regressions
careers@leadsoc.com Mail

Job Description

B.Tech or M.Tech in Computers / Electronics Engineering with minimum of 3 to 15 years of strong, hands on Data Structures and Algorithmic skills.

Skills Required

  • Solid C/C++ programming, data structure and algorithmic skills
  • Decent debugging, problem solving skills
  • Experience in performance analysis, embedded systems (not drivers, BIOS, BSP etc)
  • Other key words: FFT, Linear algebra, SIMD, optimizations, x86 assembly programming
careers@leadsoc.com Mail

Job Description

Responsible for design and development of features in LTE eNodeB for a pioneer customer in Professional Services BU. Good understanding of emerging technology and evolving specifications, understand customer requirements, ensure product quality as per internal and customerís quality requirements

Skills Required

  • Must have: Hands-on experience in LTE Access stratum protocols (MAC, RRC, RLC, and PDCP)
  • Solid knowledge of LTE Access Stratum protocol layers and procedures required
  • Prior experience in leading LTE feature design and development required
  • Has strong hands-on experience in C programming language
  • Development and testing in Unix/Linux environment
  • Knowledge of development and debugging tools required
  • Knowledge of multi-thread programming required
  • Exposure to Agile methodologies in software development is a plus
  • Exposure to configuration management tools such as Clearcase/ Git